This invention relates to logic circuitry for fabrication in customized integrated circuits, and it relates, more particularly, to circuit arrangements suitable for being integrated into basic building blocks also referred to as macros or macrocells in the context of semiconductor integrated devices of the types referred to as standard, semicustom, and full custom designs.
Gate arrays have been well-known in the art. More recently, gate arrays take the form of semiconductor integrated devices which are customizable by the user to form a plurality of customized electrical circuits. Each electrical circuit is a logic unit or a macro, such as a logic gate, (AND, NAND, OR, NOR, etc.) or a more complex logic unit such as latch, flip-flop, adder, etc. The gate arrays are customized both to form the logic units and to interconnect the logic units since there are several macros on a chip. Hereinafter, the customized connection to form a logic unit will be referred to as the intra-cell connection. The customized connection between the logic units or macros will be referred to as the inter-cell connection or wiring. In this context, the invention primarily concerns the intra-cell connections.
One of the more common forms of logic families in use is known as emitter-coupled logic (ECL). ECL circuitry provides one of the basic approaches in fabricating bipolar gate arrays. Some of the chief advantageous characteristics of practical implementations of ECL, usually in integrated circuit form, are: high speed since transistors do not saturate, high input resistance and very low output resistance for large fan out capability, very low noise generation, and the ability of using multiple levels of current switches (series gating) for complex logic functions. Notwithstanding the foregoing advantages compared to another logic family known as current-mode logic (CML), ECL has higher power dissipation and lower circuit density which requires greater area, "silicon real estate", on the chip for implementation.
CML is not as widely used as ECL, in spite of being well known, due to its disadvantage of lower driving capability. This disadvantage is apparent considering that one virtually never interfaces CML externally from an integrated circuit, but is now mainly a disadvantage within the chip itself due to high scales of integration complexity routinely utilized. In the latter situation, the distributed and parasitic capacitance involved severely detracts from the practical usefulness of CML.